A bus-hold circuit allows a bus to be held at a selected voltage level. It is desirable that leakage current from a path through the power source terminals of a device not be allowed to flow in connection with a power-out condition for the circuit. In such a situation, the current could effectively result in causing a short to circuit ground from the power supply which could ground or unnecessarily load the bus. Ioff is defined as the maximum leakage current into/out of the input/output transistors when forcing the input/output to a given DC voltage with the circuit supply voltage being equal to zero. An Ioff test simulates the power-out condition by taking the circuit supply voltage to zero and measuring the current along a path from the input terminal to a bus to the circuit power supply. This power-out condition can be caused in connection with deliberately saving power to various application devices which may be connected to a bus such as a printer, or power-out can be brought about by a malfunction of an application.
Prior art bus-hold circuits introduce Schottky diodes in the current path of the bus-hold circuit. This is undesirable since Schottky diodes can introduce leakage current by nature. This is incongruous to the favored characteristic of CMOS (complementary metal-oxide-semiconductor) of extremely low standby current. Additionally, some CMOS technologies are implemented by processes which cannot adequately process Schottky diodes. Also as the supply voltage becomes lower (i.e. 2.5 v, 1.8 v), the voltage drop across the diode will become more of a factor on the current needed for the given bus-hold current specification.
FIG. 1 is a schematic drawing of a prior art CMOS bus-hold circuit having a Schottky diode. Bus 2 is connected to input 4 and electrostatic discharge circuit 6 couple to bus-hold circuit 8. Inverter 10 comprising p-channel transistor 12 and n-channel transistor 14 with common connections between respective gates and drains, is coupled to input 4 and output 16. Inverter 18 comprising p-channel transistor 20 and n-channel transistor 22 with common connections between respective gates and drains, is connected to output 16 at the input of inverter 18 (the gates of transistors 20 and 22). Together inverter 10 and 18 serve as a latch. Schottky diode 24 through resistor 26 provides a path through which bus-hold circuit 8 can latch data on bus 2. Schottky diode 24 lessens the likelihood of significant Ioff current in a path from input 4 to Vdd during a power-out condition. However, during normal bus-hold operation of circuit 8, Schottky diode 24 limits the rail-to-rail operation of the bus due to the voltage drop which can occur across diode 24. Diode 24's voltage drop becomes more of a factor as the supply voltage becomes lower (i.e. Vdd 2.5 v, 1.8 v). The latching operation of the bus-hold circuit occurs when a logic one or logic zero is input to the gates of transistors 12 and 14 of inverter 10. An inverted state at output 16 of inverter 10 is input to inverter 18 which produces a logic state which is an inversion of the logic state at output 16. This state holds the logic on bus 2.